A semiconductor memory device generally has a large number of memory cells arranged in a matrix formation within one semiconductor chip and an address signal is applied to select a desired memory cell to write a data item in this memory cell or read the data item stored therein. FIG. 2 shows a conventional arrangement of bit lines in a DRAM (dynamic randomaccess memory) of the type with pairs of bit lines. Many bit line pairs (B.sub.1 ', B.sub.1 '), (B.sub.2 ', B.sub.2 '), etc. are disposed parallel to one another and many mutually parallel word lines W.sub.1 ', W.sub.2 ', etc. are disposed perpendicularly to these bit line pairs, memory cells MC.sub.11 ', MC.sub.12 ', etc. being connected to each crossing point between a bit line pair and a word line. In addition, there are signal lines .phi..sub.1 ', .phi..sub.2 ', etc. made of a different material from the bit lines and each disposed with one of the bit line pairs. They are used for controlling a bit line selection circuit BS' and also for other control purposes. In FIG. 2, WS' indicates a word line selection circuit, SA.sub.1 ', SA.sub.2 ', etc. indicate sense amplifiers and D' indicates data. When one of the memory cells is selected and the data item stored therein is read, the small voltage difference generated between the corresponding bit lines B.sub.i 'and B.sub.i ' is amplified by the associated sense amplifier SA.sub.i '. Since it is desirable in this situation that the parasitic capacitances of the lines B.sub.i 'and B.sub.i ' be as closely equal to each other as possible, the corresponding signal line .phi..sub.i ' is so laid out as to be at the center of this bit line pair (B.sub.i ', B.sub.i ') such that the inter-line capacitances between the bit lines B.sub.i ' and B.sub.i ' and the signal line .phi..sub.i ' are also equal to each other. In reality, however, misalignments and errors in matching mask positions are inevitable in the production of semiconductor devices. As a result, the signal line .phi..sub.i ' is closer to either of the bit lines B.sub.i 'and B.sub.i ' associated thereto and an imbalance is generated between the capacitances of the lines B.sub.i ' and B.sub.i '. This imbalance in capacitance causes the lowering of the sensitivity of the sense amplifier SA.sub.i ' and eventually the action margin of the device as a whole.